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		Addressing the timing closure problem by integrating logic optimization and placement / by Wilsin Gosti, Sunil P. Khatri and Alberto L. Sangiovanni-Vincentelli (Memorandum) by Wilsin Gosti Unknown Binding, 8 Pages, Published 2000 by Electronics Research Laboratory, College of Engineering, University of California Compare Prices \| Add to Wish List \| Set Price Alert

		Layout aware synthesis (Memorandum) by Wilsin Gosti Unknown Binding, 122 Pages, Published 2000 by Electronics Research Laboratory, College of Engineering, University of California Compare Prices \| Add to Wish List \| Set Price Alert

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