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 | | Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics (1st Edition)
by Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Hardcover, 144 Pages, Published 2001 by Springer, 1st Edition
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 | | A layout and design methodology for deep sub-micron applications using networks of PLAs (Memorandum)
by Sunil P Khatri
Unknown Binding, Published 1998 by Electronics Research Laboratory, College of Engineering, University of California
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 | | Multi-valued network compaction using redundancy removal (Memorandum)
by Sunil P Khatri
Unknown Binding, Published 1998 by Electronics Research Laboratory, College of Engineering, University of California
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 | | A VLSI design methodology using a network of PLAs embedded in a regular layout fabric (Memorandum)
by Sunil P Khatri
Unknown Binding, Published 1999 by Electronics Research Laboratory, College of Engineering, University of California
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 | | Accurate automatic timing characterization of static CMOS libraries (Memorandum)
by Sunil P Khatri
Unknown Binding, Published 1998 by Electronics Research Laboratory, College of Engineering, University of California
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 | | Addressing the timing closure problem by integrating logic optimization and placement / by Wilsin Gosti, Sunil P. Khatri and Alberto L. Sangiovanni-Vincentelli (Memorandum)
by Wilsin Gosti
Unknown Binding, 8 Pages, Published 2000 by Electronics Research Laboratory, College of Engineering, University of California
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